Sr Staff RTL Design Engineer
- Ho Chi Minh, Vietnam
- Full-time
- Employment Type: Regular (PERM)
- Remote Work Available: No
Job Description
Our team guarantee Gate netlist and SDC (Synopsys Design Constraint) qualification for Automotive SoCs. Our responsibility includes :
- RTL/Netlist qualification:
- Perform LSI ChipTop netlist check such as VC Spyglass CDC, Renesas In House Tool such as FalseCheck for asynchoronus design
- Monitor and control error judgement progress
- SDC management for each of milestone
- Hierarchical SDC creation
- IPs level constraint integration
- Delivery SDC data to other design team with high quality
- Support debugging for project members
- Monitor and control GCA (Galaxy constraint analysis) and PTE (PrimeTime error), Tempus Error/Warning judgement progress
- ECO timing
- Work with other design teams (DFT, ME/STA, BE/Layout) to develop schedule and solve problem for timing closure until TapeOut
Qualifications
- Masters or Bachelor degree in Electrical or Computer Engineering.
- Can Circuit/schematic analysis for SDC debugging and asynchoronus design
- Have STA (Static Timing Analysis) experience
- Good communication skills as well as problem solving skills.
- Ability to work under pressure and multitask.
- Experienced in Cadence tools (Tempus tool), Synopsys tools (VC Spyglass CDC tool, PrimeTime tool , RTLA tool)
- Experience in scripting languages such as C-Shell, Python, Perl, Tcl, Visual Basic
- Good at management by Ms.Office tool such as Excel skill.
